The present application relates to test system formatters for testing integrated circuit devices.
Test systems for testing high-speed integrated-circuit devices, such as microprocessors and microcontrollers, have become increasingly sophisticated due to high-speed requirements. To test high-speed devices, conventional test systems generate multiple high-frequency timing signals in order to format signals for each of the device under test (DUT) pins being tested. Each timing signal appears either as a low-to-high voltage transition (a “rising edge”) or a high-to-low voltage transition (a “falling edge”). The circuitry used to generate these timing signals generally may be divided into two portions: A first portion, called the “timing marker generator circuit” or an “edge generator circuit,” which determines the exact time for the signal transition (i.e., the “timing marker” or “timing edge”), and a second portion, called the “formatter,” which applies the edge type (“rising edge” or “falling edge”) to the signal at the time required by the timing marker. A timing marker is a pulse, which includes a rising edge immediately followed by a falling edge. Timing markers often are used in high-speed test systems in place of actual edge signals because signals attenuate (i.e., lose fidelity) at higher frequencies in wires of any length. A single timing marker is used to generate an edge. Timing markers fluctuate at twice the frequency of the edges they mark. However, if timing markers are distributed over four signal paths and brought together after traversing the signal transmission medium, each path fluctuation should be half that of the signal ultimately generated. Therefore, transmitting timing markers to generate edges is beneficial if very high-speed signals are required at the DUT pins.
FIG. 1 shows a conventional test system 114, such as the ITS9000KX system made by Schlumberger Technologies, Inc. A central processing unit (CPU) 108 is connected to a sequence control and pattern generation subsystem (Control/Pattern) 112, which has a system clock and other circuitry for generating timing markers. These timing markers are transmitted to the formatter 110, which typically plays a role in establishing the accuracy and functionality of the test system 114. In conventional test systems, the formatter 110 generally is a dedicated resource per DUT pin 118 and is configured to drive or strobe at a fixed frequency, usually the system frequency. The formatter 110 generally includes two complementary formatter circuits—a drive circuit 140 for generating test signals to be applied to the DUT and a response circuit 160 for receiving the signals outputted by the DUT. The drive circuit 140 and response circuit 160 generally can be implemented in a 0.8 micron Silicon bipolar NPN-only ECL process. However, other CMOS processes could be used to achieve substantially the same or better results.
The drive circuit 140 outputs accurate timing edges, formatted signals or a combination of both. In general, conventional drive circuits operate in a single mode, i.e., any given drive circuit outputs certain signals from a family of typically six signals, which may include two formatted signals, such as DHI and DINH, and four timing markers, such as SetHi, SetLo, SetOn and SetZ. For example, the drive circuit 140 may be configured to output formatted signals DHI and DINH to the pin-electronics circuit (PEC) 120. Alternatively, the drive circuit 140 could have been designed to output the formatted signal DINH and the timing markers SetHi and SetLo, which together define DHI. The PEC 120 uses formatted signals DHI and DINH, or their markers depending on which are provided, to determine whether to drive the DUT pin 118 to a predefined logic state, such as high, low, or tri-state, or to receive an output signal from the DUT pin 118.
The response circuit 160 generates timing markers, such as StbHi, StbLo, StbOff, and StbZ, which are used with event type information to strobe the signals ACH and BCL, provided by the pin-electronics comparator 124, to determine whether the DUT pin 118 passes or fails a test. If the state of signals ACH and BCL are different from that which is indicated by the event type, a “fail” signal is generated and outputted at STFL 162.
FIG. 2 shows a formatter 210 in which the drive circuit 240 is designed to output timing markers SetHi, SetLo, SetOn, and SetZ to external circuitry 250. The timing markers SetHi and SetLo are used by external circuitry 250 to reproduce formatted signal DHI, while timing markers SetOn and SetZ are used by external circuitry 250 to reproduce formatted signal DINH. The operation of this is as follows: SetHi sets the state of signal DHI to 1; SetLo sets the state of signal DHI to 0; SetZ sets the state of signal DINH to 1; and SetOn sets the state of signal DINH to 0.
In general, conventional systems provide a family of timing markers assigned to specific roles in the formatting of signals for each of the DUT pins to be tested. In some test systems, the family of timing markers includes three drive markers and three strobe markers. In other test systems, the family of edges includes six drive markers and four strobe markers, or four drive markers (e.g., SetHi, SetLo, SetOn, and SetZ) and four strobe markers (e.g., StbHi, StbLo, StbEnd, and StbZ). In this latter test system, for example, the drive circuit generates four timing markers with each timing marker having a data rate up to 200 MTPS (mega transitions per second). The four timing markers are used to format a signal with edge rates up to 800 MTPS. The resulting formatted signal is transmitted to a pin-electronics circuit, which then provides the signal to the DUT pin. In the same test system, the response circuit generates four edges, which are used to strobe the waveform provided by the pin-electronics comparator at rates up to 800 MTPS.
When the family of edges provided for a given pin is not fast enough to generate the waveform required for a DUT pin, some test systems use a combination of the timing markers in order to double the rate at which timed edges can be applied. For example, in these test systems, two drive circuits are externally gated to generate edge signals, which are used to create a waveform with edge rates up to 1600 MTPS. Similarly, two response circuits are externally gated to generate edges, which are used to strobe the waveform provided by the pin-electronics comparator at the rates up to 1600 MTPS.